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TTTC's Electronic Broadcasting
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Test Track at DATE 2006 |
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CALL FOR
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The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together design automation researchers, users and vendors, as well as specialists in the design, test, and manufacturing of electronic systems and circuits. One of the tracks of DATE is devoted to Methods, Tools and Innovative Experiences in Testing Electronic Circuits and Systems. At DATE 2006, we aim at the increase in the test area, and would really like to invite you to submit your contributions to the test track. This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops, as well as a Designers’ Forum. DATE is also Europe’s leading commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information. | |
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The test track is organized in six topics. These topics together with their chairs and area descriptions are given as follows. C1 Defect-Based
Testing and Test of Regular Structures Defect-based testing including non-visual, physical level, and parameter variation considerations: defect modeling, defect diagnosis, failure analysis, yield analysis, parameter variation induced faults, fault modeling, IDDx testing, Very Low Voltage testing, multiparameter testing, temperature testing, signal integrity and test methods analysis. Test techniques for regular structures such as RAM, FPGA, EEPROM, and flash memory. C2 Analogue,
Mixed-Signal, RF and Mixed-Technology Test Analogue and mixed-signal test techniques; low cost test of RF and multi-GHz electronics; testing of embedded MEMs/bio-MEMs/optics sensors and sensor electronics; fault modeling and fault coverage metrics; test stimulus generation and response analysis; design-for-testability (DFT) and built-in self-test (BIST); self-calibration for BIST; case studies on the application of advanced test methods to industrial ICs and SoCs. C3 Test
Generation, Simulation and Diagnosis Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs. C4 Design for
Test and BIST Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures. C5 Hierarchical,
System, and Industrial Test Testing throughout various hierarchy levels: embedded cores, System-on-Chip, System-in-Package, board, system; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor-based test; infrastructure IP. Industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies. C6 On-Line
Testing, Fault Tolerance, and Reliability Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; robust design; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; high reliability systems; reliability and dependability evaluation; safety; security; availability; reliability; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications. | |
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All manuscripts must be submitted for review electronically, following the instructions on the conference Web page: The
accepted file formats are PDF and Postscript. Manuscripts received in
hard-copy form will not be processed.
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Prof. Zebo Peng
- DATE Test Track Chair Prof. Donatella
Sciuto - DATE Program Chair | |
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For more information, visit us on the web
at: http://www.date-conference.com/ | |
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The Design, Automation and Test in Europe Conference (DATE 2006) is sponsored by the European Design and Automation Association, the EDA Consortium, the IEEE Computer Society - TTTC, ECSI, RAS and ACM SIGDA. | |
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IEEE Computer Society– Test Technology
Technical Council | ||
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TTTC CHAIR SENIOR PAST CHAIR
FINANCE CHAIR IEEE DESIGN & TEST
EIC TECHNICAL MEETINGS TECHNICAL ACTIVITIES ASIA & SOUTH PACIFIC LATIN AMERICA NORTH AMERICA COMMUNICATIONS INDUSTRY ADVISORY BOARD |
PAST CHAIR TTTC 1ST VICE CHAIR SECRETARY ITC GENERAL CHAIR TEST WEEK COORDINATOR TUTORIALS AND EDUCATION STANDARDS EUROPE MIDDLE EAST & AFRICA STANDING COMMITTEES ELECTRONIC MEDIA | |
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